Index: xen-unstable.hg/xen/arch/ia64/xen/ivt.S
===================================================================
--- xen-unstable.hg.orig/xen/arch/ia64/xen/ivt.S	2007-12-10 13:55:22.000000000 +0900
+++ xen-unstable.hg/xen/arch/ia64/xen/ivt.S	2007-12-10 13:55:42.000000000 +0900
@@ -104,7 +104,71 @@ ia64_ivt:
 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
 ENTRY(vhpt_miss)
 	DBG_FAULT(0)
+#if 0
 	FAULT(0)
+#else
+	mov r16 = cr.ifa
+	;;
+	// If it is not a Xen address, handle it via page_fault.
+	//    !( r22 == 0x18 || r22 == 0x1c || r22 == 0x1e )
+	// XXX: Need to check XEN_RID
+	// XXX: Need to check psr.cpl == 0
+	extr.u r22=r16,59,5
+	;;
+	cmp.eq p8,p0=0x18,r22		// 0xc...
+	;;
+	cmp.eq.or p8,p0=0x1c,r22	// 0xe...
+	;;
+	cmp.eq.or p8,p0=0x1e,r22	// 0xf...
+	;;
+(p8)	br.cond.spnt vhpt_miss_identity_map
+	;;
+	FAULT(0)
+	;;
+
+vhpt_miss_identity_map:
+
+	// Clear key
+	mov r20=cr.itir
+	;;
+	dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN	// clear the key
+	;;
+	mov cr.itir=r20
+	;;
+
+	cmp.eq p6,p0=0x18,r22   // address == 0xc...
+	cmp.eq p7,p0=0x1c,r22   // address == 0xe...
+	movl r17=PAGE_KERNEL
+	;;
+(p6)	movl r17=(__DIRTY_BITS | _PAGE_AR_RWX | _PAGE_PL_PRIV | _PAGE_MA_UC)
+(p7)	movl r17=(__DIRTY_BITS | _PAGE_AR_RWX)
+	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
+	;;
+        and r19=r19,r16                         // clear ed, reserved bits, and
+						//  PTE control bits
+	;;
+	or r19=r19,r17          // insert PTE control bits into r19
+	;;
+
+	// XXX: Handle speculation bit ?
+	// XXX: Check isr.code field ?
+
+#if 0
+	// XXX: Is it always data ?
+	mov r20=cr.isr
+	;;
+	extr.u r20=r20,IA64_ISR_X_BIT,1
+	;;
+	cmp.eq p6,p7=r0,r20
+	;;
+
+(p6)	itc.d r19
+(p7)	itc.i r19
+#else
+	itc.d r19
+#endif
+	rfi
+#endif
 END(vhpt_miss)
 
 	.org ia64_ivt+0x400