Index: 20071119-ia64/xen/arch/ia64/xen/ivt.S
===================================================================
--- 20071119-ia64.orig/xen/arch/ia64/xen/ivt.S	2007-11-21 23:02:14.000000000 -0700
+++ 20071119-ia64/xen/arch/ia64/xen/ivt.S	2007-11-21 23:20:38.000000000 -0700
@@ -122,13 +122,17 @@
 	br.cond.spnt branch_on_xen_memory
 	;;
 itlb_miss_identity_map:
-	/* EFI PAGE size is IA64_GRANULE_SIZE
+	/* EFI memory's page size is IA64_GRANULE_SIZE
+	 * Other memory's page size is PAGE_SIZE
 	 * itir's key should be 0, as should the reserved space
-	 * thus we can just set itir = (IA64_GRANULE_SHIFT << 2)
+	 * thus we can just set itir = (X << 2)
 	 */
-	movl r20=IA64_GRANULE_SHIFT
+	cmp.eq p6,p0=0x18,r22   // address == 0xe...
+	cmp.eq p7,p0=0x1c,r22   // address == 0xf...
+	movl r20=(PAGE_SHIFT << 2)
 	;;
-	shl r20=r20,2
+(p6)	movl r20=(IA64_GRANULE_SHIFT << 2)
+(p7)	movl r20=(IA64_GRANULE_SHIFT << 2)
 	;;
 	mov cr.itir=r20
 	;;
@@ -176,12 +180,17 @@
 (p8)	br.cond.sptk fast_tlb_miss_reflect
 	;;
 
-	// EFI PAGE size is IA64_GRANULE_SIZE
-	// itir's key should be 0, as should the reserved space
-	// thus we can just set itir = (IA64_GRANULE_SHIFT << 2)
-	movl r20=IA64_GRANULE_SHIFT
+	/* EFI memory's page size is IA64_GRANULE_SIZE
+	 * Other memory's page size is PAGE_SIZE
+	 * itir's key should be 0, as should the reserved space
+	 * thus we can just set itir = (X << 2)
+	 */
+	cmp.eq p6,p0=0x18,r22   // address == 0xe...
+	cmp.eq p7,p0=0x1c,r22   // address == 0xf...
+	movl r20=(PAGE_SHIFT << 2)
 	;;
-	shl r20=r20,2
+(p6)	movl r20=(IA64_GRANULE_SHIFT << 2)
+(p7)	movl r20=(IA64_GRANULE_SHIFT << 2)
 	;;
 	mov cr.itir=r20
 	;;
@@ -195,7 +204,7 @@
 	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
 	;;
 	and r19=r19,r16         // clear ed, reserved bits, and PTE ctrl bits
-  	;;
+	;;
 	or r19=r17,r19          // insert PTE control bits into r19
 	;;
 
@@ -231,8 +240,10 @@
 (p6)	movl r17=(__DIRTY_BITS | _PAGE_AR_RWX | _PAGE_PL_PRIV | _PAGE_MA_UC)
 (p7)	movl r17=(__DIRTY_BITS | _PAGE_AR_RWX)
 	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
+	movl r20=(PAGE_SHIFT << 2)
 	;;
-	mov r20=cr.itir
+(p6)	movl r20=(IA64_GRANULE_SHIFT << 2)
+(p7)	movl r20=(IA64_GRANULE_SHIFT << 2)
 	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
 	and r19=r19,r16		// clear ed, reserved bits, and PTE ctrl bits
 	extr.u r18=r16,XEN_VIRT_UC_BIT,1	// extract UC bit
@@ -323,11 +334,15 @@
 						//   PTE control bits
 	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
 	;;
+	movl r20=(PAGE_SHIFT << 2)
+	;;
+(p6)	movl r20=(IA64_GRANULE_SHIFT << 2)
+(p7)	movl r20=(IA64_GRANULE_SHIFT << 2)
+	;;
 	cmp.ne p8,p0=r0,r23
 (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
 (p8)	br.cond.spnt page_fault
 	;;
-	mov r20=cr.itir
 #ifdef CONFIG_VIRTUAL_FRAME_TABLE
 	shr r22=r16,56	 	// Test for the address of virtual frame_table
 	;;
@@ -337,7 +352,6 @@
 	movl r26=alt_dtlb_miss_identity_map
 	movl r27=page_fault
 	;;
-	dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN	// clear the key
 	br.cond.spnt branch_on_xen_memory
 	;;
 alt_dtlb_miss_identity_map:
@@ -347,7 +361,7 @@
 	;;
 	cmp.ne p8,p0=r0,r18		// Xen UC bit set
 	;;
-	cmp.eq.or p8,p0=0x18,r22 	// Region 6 is UC for EFI
+	cmp.eq.or p8,p0=0x18,r22	// Region 6 is UC for EFI
 	;;
 (p8)	dep r19=-1,r19,4,1	// set bit 4 (uncached) if access to UC area